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The 6-inch Silicon Carbide (SiC) wafer is a next-generation semiconductor substrate designed for high-power, high-temperature, and high-frequency electronic applications. With superior thermal conductivity, wide bandgap, and chemical stability, SiC wafers enable the fabrication of advanced power devices that deliver higher efficiency, greater reliability, and smaller footprints compared to traditional silicon-based technologies.
SiC’s wide bandgap (~3.26 eV) allows electronic devices to operate at voltages exceeding 1,200 V, temperatures above 200°C, and switching frequencies several times higher than silicon. The 6-inch format offers a balanced combination of manufacturing scalability and cost-effectiveness, making it the mainstream size for industrial mass production of SiC MOSFETs, Schottky diodes, and epitaxial wafers.
The 6-inch SiC wafer is grown using Physical Vapor Transport (PVT) or Sublimation Growth Technology. In this process, high-purity SiC powder is sublimed at temperatures exceeding 2,000°C and recrystallized onto a seed crystal under precisely controlled thermal gradients. The resulting single-crystal SiC boule is then sliced, lapped, polished, and cleaned to achieve wafer-grade flatness and surface quality.
For device fabrication, epitaxial layers are deposited on the wafer surface via Chemical Vapor Deposition (CVD), enabling precise control over doping concentration and layer thickness. This ensures uniform electrical performance and minimal crystal defects across the entire wafer surface.
Wide Bandgap (3.26 eV): Enables high-voltage operation and superior power efficiency.
High Thermal Conductivity (4.9 W/cm·K): Ensures efficient heat dissipation for high-power devices.
High Breakdown Electric Field (3 MV/cm): Allows thinner device structures with lower leakage current.
High Electron Saturation Velocity: Supports high-frequency switching and faster response times.
Excellent Chemical & Radiation Resistance: Ideal for harsh environments such as aerospace and energy systems.
Larger Diameter (6-inch): Improves wafer yield and lowers per-device cost in mass production.
SiC in AR Glasses:
SiC materials improve power efficiency, reduce heat generation, and enable thinner, lighter AR systems through high thermal conductivity and wide bandgap properties.
SiC in MOSFETs:
SiC MOSFETs provide fast switching, high breakdown voltage, and low loss, making them ideal for microdisplay drivers and laser projection power circuits.
SiC in SBDs:
SiC Schottky Barrier Diodes offer ultra-fast rectification and low reverse recovery loss, enhancing charging and DC/DC converter efficiency in AR glasses.
6inch 4H-N type SiC wafer's specification |
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| Property | Zero MPD Production Grade (Z Grade) | Dummy Grade (D Grade) |
| Grade | Zero MPD Production Grade (Z Grade) | Dummy Grade (D Grade) |
| Diameter | 149.5 mm - 150.0 mm | 149.5 mm - 150.0 mm |
| Poly-type | 4H | 4H |
| Thickness | 350 µm ± 15 µm | 350 µm ± 25 µm |
| Wafer Orientation | Off axis: 4.0° toward <1120> ± 0.5° | Off axis: 4.0° toward <1120> ± 0.5° |
| Micropipe Density | ≤ 0.2 cm² | ≤ 15 cm² |
| Resistivity | 0.015 - 0.024 Ω·cm | 0.015 - 0.028 Ω·cm |
| Primary Flat Orientation | [10-10] ± 50° | [10-10] ± 50° |
| Primary Flat Length | 475 mm ± 2.0 mm | 475 mm ± 2.0 mm |
| Edge Exclusion | 3 mm | 3 mm |
| LTV/TIV / Bow / Warp | ≤ 2.5 µm / ≤ 6 µm / ≤ 25 µm / ≤ 35 µm | ≤ 5 µm / ≤ 15 µm / ≤ 40 µm / ≤ 60 µm |
| Roughness | Polish Ra ≤ 1 nm | Polish Ra ≤ 1 nm |
| CMP Ra | ≤ 0.2 nm | ≤ 0.5 nm |
| Edge Cracks By High Intensity Light | Cumulative length ≤ 20 mm single length ≤ 2 mm | Cumulative length ≤ 20 mm single length ≤ 2 mm |
| Hex Plates By High Intensity Light | Cumulative area ≤ 0.05% | Cumulative area ≤ 0.1% |
| Polytype Areas By High Intensity Light | Cumulative area ≤ 0.05% | Cumulative area ≤ 3% |
| Visual Carbon Inclusions | Cumulative area ≤ 0.05% | Cumulative area ≤ 5% |
| Silicon Surface Scratches By High Intensity Light | Cumulative length ≤ 1 wafer diameter | |
| Edge Chips By High Intensity Light | None permitted ≥ 0.2 mm width and depth | 7 allowed, ≤ 1 mm each |
| Threading Screw Dislocation | < 500 cm³ | < 500 cm³ |
| Silicon Surface Contamination By High Intensity Light | ||
| Packaging | Multi-wafer Cassette Or Single Wafer Container | Multi-wafer Cassette Or Single Wafer Container |
High Yield and Low Defect Density: Advanced crystal growth process ensures minimal micropipes and dislocations.
Stable Epitaxy Capability: Compatible with multiple epitaxial and device manufacturing processes.
Customizable Specifications: Available in various orientations, doping levels, and thicknesses.
Strict Quality Control: Full inspection via XRD, AFM, and PL mapping to guarantee uniformity.
Global Supply Chain Support: Reliable production capacity for both prototype and volume orders.
Q1: What’s the difference between 4H-SiC and 6H-SiC wafers?
A1: 4H-SiC offers higher electron mobility and is preferred for high-power, high-frequency devices, while 6H-SiC is suitable for applications requiring higher breakdown voltage and lower cost.
Q2: Can the wafer be supplied with an epitaxial layer?
A2: Yes. Epitaxial SiC wafers (epi-wafers) are available with custom thickness, doping type, and uniformity according to device requirements.
Q3: How does SiC compare to GaN and Si materials?
A3: SiC supports higher voltages and temperatures than GaN or Si, making it ideal for high-power systems. GaN is better suited for high-frequency, low-voltage applications.
Q4: What surface orientations are commonly used?
A4: The most common orientations are (0001) for vertical devices and (11-20) or (1-100) for lateral device structures.
Q5: What is the typical lead time for 6-inch SiC wafers?
A5: Standard lead time is approximately 4–6 weeks, depending on specifications and order volume.
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